-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"

-- DATE "04/12/2021 16:35:20"

-- 
-- Device: Altera EP3C40F780C8 Package FBGA780
-- 

-- 
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
-- 

LIBRARY ALTERA;
LIBRARY CYCLONEIII;
LIBRARY IEEE;
USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY 	keyboard IS
    PORT (
	clk : IN std_logic;
	key_R : IN std_logic_vector(3 DOWNTO 0);
	key_C : OUT std_logic_vector(3 DOWNTO 0);
	codeout : OUT std_logic_vector(7 DOWNTO 0)
	);
END keyboard;

-- Design Ports Information
-- key_C[0]	=>  Location: PIN_G13,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- key_C[1]	=>  Location: PIN_B11,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- key_C[2]	=>  Location: PIN_A11,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- key_C[3]	=>  Location: PIN_A10,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- codeout[0]	=>  Location: PIN_C10,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- codeout[1]	=>  Location: PIN_F11,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- codeout[2]	=>  Location: PIN_H13,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- codeout[3]	=>  Location: PIN_K13,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- codeout[4]	=>  Location: PIN_H12,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- codeout[5]	=>  Location: PIN_B8,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- codeout[6]	=>  Location: PIN_D11,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- codeout[7]	=>  Location: PIN_U28,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- key_R[1]	=>  Location: PIN_J12,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- key_R[2]	=>  Location: PIN_E14,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- key_R[0]	=>  Location: PIN_B10,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- key_R[3]	=>  Location: PIN_F14,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- clk	=>  Location: PIN_J2,	 I/O Standard: 2.5 V,	 Current Strength: Default


ARCHITECTURE structure OF keyboard IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_key_R : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_key_C : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_codeout : std_logic_vector(7 DOWNTO 0);
SIGNAL \clk~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \div_clk~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \key_C[0]~output_o\ : std_logic;
SIGNAL \key_C[1]~output_o\ : std_logic;
SIGNAL \key_C[2]~output_o\ : std_logic;
SIGNAL \key_C[3]~output_o\ : std_logic;
SIGNAL \codeout[0]~output_o\ : std_logic;
SIGNAL \codeout[1]~output_o\ : std_logic;
SIGNAL \codeout[2]~output_o\ : std_logic;
SIGNAL \codeout[3]~output_o\ : std_logic;
SIGNAL \codeout[4]~output_o\ : std_logic;
SIGNAL \codeout[5]~output_o\ : std_logic;
SIGNAL \codeout[6]~output_o\ : std_logic;
SIGNAL \codeout[7]~output_o\ : std_logic;
SIGNAL \clk~input_o\ : std_logic;
SIGNAL \clk~inputclkctrl_outclk\ : std_logic;
SIGNAL \count[0]~6_combout\ : std_logic;
SIGNAL \LessThan0~0_combout\ : std_logic;
SIGNAL \LessThan0~1_combout\ : std_logic;
SIGNAL \count[0]~7\ : std_logic;
SIGNAL \count[1]~8_combout\ : std_logic;
SIGNAL \count[1]~9\ : std_logic;
SIGNAL \count[2]~10_combout\ : std_logic;
SIGNAL \count[2]~11\ : std_logic;
SIGNAL \count[3]~12_combout\ : std_logic;
SIGNAL \count[3]~13\ : std_logic;
SIGNAL \count[4]~14_combout\ : std_logic;
SIGNAL \count[4]~15\ : std_logic;
SIGNAL \count[5]~16_combout\ : std_logic;
SIGNAL \div_clk~0_combout\ : std_logic;
SIGNAL \div_clk~feeder_combout\ : std_logic;
SIGNAL \div_clk~q\ : std_logic;
SIGNAL \div_clk~clkctrl_outclk\ : std_logic;
SIGNAL \Mux1~0_combout\ : std_logic;
SIGNAL \key_R[3]~input_o\ : std_logic;
SIGNAL \key_R[2]~input_o\ : std_logic;
SIGNAL \key_R[0]~input_o\ : std_logic;
SIGNAL \key_R[1]~input_o\ : std_logic;
SIGNAL \Equal0~0_combout\ : std_logic;
SIGNAL \key_C[2]~reg0_q\ : std_logic;
SIGNAL \Mux0~0_combout\ : std_logic;
SIGNAL \key_C[3]~reg0_q\ : std_logic;
SIGNAL \Mux2~0_combout\ : std_logic;
SIGNAL \key_C[1]~reg0_q\ : std_logic;
SIGNAL \Mux3~0_combout\ : std_logic;
SIGNAL \key_C[0]~reg0_q\ : std_logic;
SIGNAL \Equal0~1_combout\ : std_logic;
SIGNAL \Selector6~0_combout\ : std_logic;
SIGNAL \Selector6~1_combout\ : std_logic;
SIGNAL \codeout[0]~2_combout\ : std_logic;
SIGNAL \codeout[0]~3_combout\ : std_logic;
SIGNAL \codeout[0]~4_combout\ : std_logic;
SIGNAL \codeout[0]~reg0_q\ : std_logic;
SIGNAL \codeout[0]~5_combout\ : std_logic;
SIGNAL \Selector5~0_combout\ : std_logic;
SIGNAL \Selector5~1_combout\ : std_logic;
SIGNAL \codeout[1]~reg0_q\ : std_logic;
SIGNAL \Selector4~0_combout\ : std_logic;
SIGNAL \codeout[2]~0_combout\ : std_logic;
SIGNAL \codeout[0]~5_wirecell_combout\ : std_logic;
SIGNAL \codeout[2]~reg0_q\ : std_logic;
SIGNAL \Selector3~0_combout\ : std_logic;
SIGNAL \Selector3~1_combout\ : std_logic;
SIGNAL \codeout[3]~reg0_q\ : std_logic;
SIGNAL \Selector2~2_combout\ : std_logic;
SIGNAL \Selector2~0_combout\ : std_logic;
SIGNAL \Selector2~1_combout\ : std_logic;
SIGNAL \Selector2~3_combout\ : std_logic;
SIGNAL \codeout[4]~reg0_q\ : std_logic;
SIGNAL \codeout[5]~1_combout\ : std_logic;
SIGNAL \codeout[5]~reg0_q\ : std_logic;
SIGNAL \Selector0~0_combout\ : std_logic;
SIGNAL \Selector0~1_combout\ : std_logic;
SIGNAL \codeout[6]~reg0_q\ : std_logic;
SIGNAL count : std_logic_vector(5 DOWNTO 0);
SIGNAL \ALT_INV_key_C[3]~reg0_q\ : std_logic;
SIGNAL \ALT_INV_key_R[3]~input_o\ : std_logic;

BEGIN

ww_clk <= clk;
ww_key_R <= key_R;
key_C <= ww_key_C;
codeout <= ww_codeout;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

\clk~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \clk~input_o\);

\div_clk~clkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \div_clk~q\);
\ALT_INV_key_C[3]~reg0_q\ <= NOT \key_C[3]~reg0_q\;
\ALT_INV_key_R[3]~input_o\ <= NOT \key_R[3]~input_o\;

-- Location: IOOBUF_X25_Y43_N30
\key_C[0]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \key_C[0]~reg0_q\,
	devoe => ww_devoe,
	o => \key_C[0]~output_o\);

-- Location: IOOBUF_X25_Y43_N9
\key_C[1]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \key_C[1]~reg0_q\,
	devoe => ww_devoe,
	o => \key_C[1]~output_o\);

-- Location: IOOBUF_X25_Y43_N2
\key_C[2]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \key_C[2]~reg0_q\,
	devoe => ww_devoe,
	o => \key_C[2]~output_o\);

-- Location: IOOBUF_X25_Y43_N16
\key_C[3]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \key_C[3]~reg0_q\,
	devoe => ww_devoe,
	o => \key_C[3]~output_o\);

-- Location: IOOBUF_X22_Y43_N16
\codeout[0]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \codeout[0]~reg0_q\,
	devoe => ww_devoe,
	o => \codeout[0]~output_o\);

-- Location: IOOBUF_X22_Y43_N30
\codeout[1]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \codeout[1]~reg0_q\,
	devoe => ww_devoe,
	o => \codeout[1]~output_o\);

-- Location: IOOBUF_X22_Y43_N2
\codeout[2]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \codeout[2]~reg0_q\,
	devoe => ww_devoe,
	o => \codeout[2]~output_o\);

-- Location: IOOBUF_X27_Y43_N2
\codeout[3]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \codeout[3]~reg0_q\,
	devoe => ww_devoe,
	o => \codeout[3]~output_o\);

-- Location: IOOBUF_X27_Y43_N23
\codeout[4]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \codeout[4]~reg0_q\,
	devoe => ww_devoe,
	o => \codeout[4]~output_o\);

-- Location: IOOBUF_X22_Y43_N9
\codeout[5]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \codeout[5]~reg0_q\,
	devoe => ww_devoe,
	o => \codeout[5]~output_o\);

-- Location: IOOBUF_X22_Y43_N23
\codeout[6]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \codeout[6]~reg0_q\,
	devoe => ww_devoe,
	o => \codeout[6]~output_o\);

-- Location: IOOBUF_X67_Y15_N2
\codeout[7]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \codeout[7]~output_o\);

-- Location: IOIBUF_X0_Y21_N1
\clk~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_clk,
	o => \clk~input_o\);

-- Location: CLKCTRL_G4
\clk~inputclkctrl\ : cycloneiii_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
	inclk => \clk~inputclkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \clk~inputclkctrl_outclk\);

-- Location: LCCOMB_X34_Y42_N18
\count[0]~6\ : cycloneiii_lcell_comb
-- Equation(s):
-- \count[0]~6_combout\ = count(0) $ (VCC)
-- \count[0]~7\ = CARRY(count(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001111001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => count(0),
	datad => VCC,
	combout => \count[0]~6_combout\,
	cout => \count[0]~7\);

-- Location: LCCOMB_X34_Y42_N0
\LessThan0~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \LessThan0~0_combout\ = ((!count(2) & (!count(1) & !count(3)))) # (!count(4))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100011111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => count(2),
	datab => count(1),
	datac => count(4),
	datad => count(3),
	combout => \LessThan0~0_combout\);

-- Location: LCCOMB_X34_Y42_N8
\LessThan0~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \LessThan0~1_combout\ = (count(5) & !\LessThan0~0_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => count(5),
	datad => \LessThan0~0_combout\,
	combout => \LessThan0~1_combout\);

-- Location: FF_X34_Y42_N19
\count[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \count[0]~6_combout\,
	sclr => \LessThan0~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => count(0));

-- Location: LCCOMB_X34_Y42_N20
\count[1]~8\ : cycloneiii_lcell_comb
-- Equation(s):
-- \count[1]~8_combout\ = (count(1) & (!\count[0]~7\)) # (!count(1) & ((\count[0]~7\) # (GND)))
-- \count[1]~9\ = CARRY((!\count[0]~7\) # (!count(1)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => count(1),
	datad => VCC,
	cin => \count[0]~7\,
	combout => \count[1]~8_combout\,
	cout => \count[1]~9\);

-- Location: FF_X34_Y42_N21
\count[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \count[1]~8_combout\,
	sclr => \LessThan0~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => count(1));

-- Location: LCCOMB_X34_Y42_N22
\count[2]~10\ : cycloneiii_lcell_comb
-- Equation(s):
-- \count[2]~10_combout\ = (count(2) & (\count[1]~9\ $ (GND))) # (!count(2) & (!\count[1]~9\ & VCC))
-- \count[2]~11\ = CARRY((count(2) & !\count[1]~9\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010010100001010",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => count(2),
	datad => VCC,
	cin => \count[1]~9\,
	combout => \count[2]~10_combout\,
	cout => \count[2]~11\);

-- Location: FF_X34_Y42_N23
\count[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \count[2]~10_combout\,
	sclr => \LessThan0~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => count(2));

-- Location: LCCOMB_X34_Y42_N24
\count[3]~12\ : cycloneiii_lcell_comb
-- Equation(s):
-- \count[3]~12_combout\ = (count(3) & (!\count[2]~11\)) # (!count(3) & ((\count[2]~11\) # (GND)))
-- \count[3]~13\ = CARRY((!\count[2]~11\) # (!count(3)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => count(3),
	datad => VCC,
	cin => \count[2]~11\,
	combout => \count[3]~12_combout\,
	cout => \count[3]~13\);

-- Location: FF_X34_Y42_N25
\count[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \count[3]~12_combout\,
	sclr => \LessThan0~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => count(3));

-- Location: LCCOMB_X34_Y42_N26
\count[4]~14\ : cycloneiii_lcell_comb
-- Equation(s):
-- \count[4]~14_combout\ = (count(4) & (\count[3]~13\ $ (GND))) # (!count(4) & (!\count[3]~13\ & VCC))
-- \count[4]~15\ = CARRY((count(4) & !\count[3]~13\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010010100001010",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => count(4),
	datad => VCC,
	cin => \count[3]~13\,
	combout => \count[4]~14_combout\,
	cout => \count[4]~15\);

-- Location: FF_X34_Y42_N27
\count[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \count[4]~14_combout\,
	sclr => \LessThan0~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => count(4));

-- Location: LCCOMB_X34_Y42_N28
\count[5]~16\ : cycloneiii_lcell_comb
-- Equation(s):
-- \count[5]~16_combout\ = \count[4]~15\ $ (count(5))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111111110000",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datad => count(5),
	cin => \count[4]~15\,
	combout => \count[5]~16_combout\);

-- Location: FF_X34_Y42_N29
\count[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \count[5]~16_combout\,
	sclr => \LessThan0~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => count(5));

-- Location: LCCOMB_X34_Y42_N30
\div_clk~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \div_clk~0_combout\ = \div_clk~q\ $ (((count(5) & !\LessThan0~0_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101001100110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \div_clk~q\,
	datab => count(5),
	datad => \LessThan0~0_combout\,
	combout => \div_clk~0_combout\);

-- Location: LCCOMB_X34_Y42_N2
\div_clk~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \div_clk~feeder_combout\ = \div_clk~0_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \div_clk~0_combout\,
	combout => \div_clk~feeder_combout\);

-- Location: FF_X34_Y42_N3
div_clk : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div_clk~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div_clk~q\);

-- Location: CLKCTRL_G10
\div_clk~clkctrl\ : cycloneiii_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
	inclk => \div_clk~clkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \div_clk~clkctrl_outclk\);

-- Location: LCCOMB_X26_Y42_N18
\Mux1~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux1~0_combout\ = (\key_C[1]~reg0_q\ & ((\key_C[0]~reg0_q\ & (\key_C[3]~reg0_q\)) # (!\key_C[0]~reg0_q\ & ((\key_C[2]~reg0_q\))))) # (!\key_C[1]~reg0_q\ & (((\key_C[2]~reg0_q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011100011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_C[3]~reg0_q\,
	datab => \key_C[1]~reg0_q\,
	datac => \key_C[2]~reg0_q\,
	datad => \key_C[0]~reg0_q\,
	combout => \Mux1~0_combout\);

-- Location: IOIBUF_X27_Y43_N8
\key_R[3]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_key_R(3),
	o => \key_R[3]~input_o\);

-- Location: IOIBUF_X27_Y43_N15
\key_R[2]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_key_R(2),
	o => \key_R[2]~input_o\);

-- Location: IOIBUF_X25_Y43_N22
\key_R[0]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_key_R(0),
	o => \key_R[0]~input_o\);

-- Location: IOIBUF_X27_Y43_N29
\key_R[1]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_key_R(1),
	o => \key_R[1]~input_o\);

-- Location: LCCOMB_X26_Y42_N14
\Equal0~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Equal0~0_combout\ = (\key_R[3]~input_o\ & (\key_R[2]~input_o\ & (\key_R[0]~input_o\ & \key_R[1]~input_o\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_R[3]~input_o\,
	datab => \key_R[2]~input_o\,
	datac => \key_R[0]~input_o\,
	datad => \key_R[1]~input_o\,
	combout => \Equal0~0_combout\);

-- Location: FF_X26_Y42_N19
\key_C[2]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \Mux1~0_combout\,
	ena => \Equal0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \key_C[2]~reg0_q\);

-- Location: LCCOMB_X26_Y42_N8
\Mux0~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux0~0_combout\ = (\key_C[1]~reg0_q\ & ((\key_C[2]~reg0_q\ & (\key_C[0]~reg0_q\)) # (!\key_C[2]~reg0_q\ & ((\key_C[3]~reg0_q\))))) # (!\key_C[1]~reg0_q\ & (((\key_C[3]~reg0_q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011100011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_C[0]~reg0_q\,
	datab => \key_C[1]~reg0_q\,
	datac => \key_C[3]~reg0_q\,
	datad => \key_C[2]~reg0_q\,
	combout => \Mux0~0_combout\);

-- Location: FF_X26_Y42_N9
\key_C[3]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \Mux0~0_combout\,
	ena => \Equal0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \key_C[3]~reg0_q\);

-- Location: LCCOMB_X26_Y42_N4
\Mux2~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux2~0_combout\ = (\key_C[0]~reg0_q\ & ((\key_C[3]~reg0_q\ & ((\key_C[2]~reg0_q\))) # (!\key_C[3]~reg0_q\ & (\key_C[1]~reg0_q\)))) # (!\key_C[0]~reg0_q\ & (((\key_C[1]~reg0_q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111100001110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_C[0]~reg0_q\,
	datab => \key_C[3]~reg0_q\,
	datac => \key_C[1]~reg0_q\,
	datad => \key_C[2]~reg0_q\,
	combout => \Mux2~0_combout\);

-- Location: FF_X26_Y42_N5
\key_C[1]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \Mux2~0_combout\,
	ena => \Equal0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \key_C[1]~reg0_q\);

-- Location: LCCOMB_X26_Y42_N10
\Mux3~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux3~0_combout\ = (\key_C[3]~reg0_q\ & ((\key_C[2]~reg0_q\ & (\key_C[1]~reg0_q\)) # (!\key_C[2]~reg0_q\ & ((\key_C[0]~reg0_q\))))) # (!\key_C[3]~reg0_q\ & (((\key_C[0]~reg0_q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011100011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_C[1]~reg0_q\,
	datab => \key_C[3]~reg0_q\,
	datac => \key_C[0]~reg0_q\,
	datad => \key_C[2]~reg0_q\,
	combout => \Mux3~0_combout\);

-- Location: FF_X26_Y42_N11
\key_C[0]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \Mux3~0_combout\,
	ena => \Equal0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \key_C[0]~reg0_q\);

-- Location: LCCOMB_X27_Y42_N12
\Equal0~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Equal0~1_combout\ = (\key_R[2]~input_o\ & \key_R[1]~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \key_R[2]~input_o\,
	datad => \key_R[1]~input_o\,
	combout => \Equal0~1_combout\);

-- Location: LCCOMB_X26_Y42_N20
\Selector6~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Selector6~0_combout\ = (\key_C[2]~reg0_q\ & ((\key_R[3]~input_o\ & ((!\key_C[1]~reg0_q\))) # (!\key_R[3]~input_o\ & (\key_C[3]~reg0_q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010000011100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_C[3]~reg0_q\,
	datab => \key_R[3]~input_o\,
	datac => \key_C[2]~reg0_q\,
	datad => \key_C[1]~reg0_q\,
	combout => \Selector6~0_combout\);

-- Location: LCCOMB_X26_Y42_N26
\Selector6~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Selector6~1_combout\ = (\Selector6~0_combout\) # ((\key_R[3]~input_o\ & ((!\Equal0~1_combout\) # (!\key_C[3]~reg0_q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111011111110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_C[3]~reg0_q\,
	datab => \Equal0~1_combout\,
	datac => \Selector6~0_combout\,
	datad => \key_R[3]~input_o\,
	combout => \Selector6~1_combout\);

-- Location: LCCOMB_X26_Y42_N30
\codeout[0]~2\ : cycloneiii_lcell_comb
-- Equation(s):
-- \codeout[0]~2_combout\ = (\key_R[3]~input_o\ & ((\key_R[2]~input_o\ & (\key_R[0]~input_o\ $ (!\key_R[1]~input_o\))) # (!\key_R[2]~input_o\ & ((!\key_R[1]~input_o\) # (!\key_R[0]~input_o\))))) # (!\key_R[3]~input_o\ & (((!\key_R[1]~input_o\) # 
-- (!\key_R[0]~input_o\)) # (!\key_R[2]~input_o\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1001011101111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_R[3]~input_o\,
	datab => \key_R[2]~input_o\,
	datac => \key_R[0]~input_o\,
	datad => \key_R[1]~input_o\,
	combout => \codeout[0]~2_combout\);

-- Location: LCCOMB_X26_Y42_N16
\codeout[0]~3\ : cycloneiii_lcell_comb
-- Equation(s):
-- \codeout[0]~3_combout\ = (\key_C[0]~reg0_q\ & ((\key_C[1]~reg0_q\ & (\key_C[3]~reg0_q\ $ (!\key_C[2]~reg0_q\))) # (!\key_C[1]~reg0_q\ & ((!\key_C[2]~reg0_q\) # (!\key_C[3]~reg0_q\))))) # (!\key_C[0]~reg0_q\ & (((!\key_C[2]~reg0_q\) # (!\key_C[3]~reg0_q\)) 
-- # (!\key_C[1]~reg0_q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1001011101111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_C[0]~reg0_q\,
	datab => \key_C[1]~reg0_q\,
	datac => \key_C[3]~reg0_q\,
	datad => \key_C[2]~reg0_q\,
	combout => \codeout[0]~3_combout\);

-- Location: LCCOMB_X26_Y42_N6
\codeout[0]~4\ : cycloneiii_lcell_comb
-- Equation(s):
-- \codeout[0]~4_combout\ = (!\codeout[0]~2_combout\ & !\codeout[0]~3_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \codeout[0]~2_combout\,
	datad => \codeout[0]~3_combout\,
	combout => \codeout[0]~4_combout\);

-- Location: FF_X26_Y42_N27
\codeout[0]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Selector6~1_combout\,
	ena => \codeout[0]~4_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \codeout[0]~reg0_q\);

-- Location: LCCOMB_X26_Y42_N2
\codeout[0]~5\ : cycloneiii_lcell_comb
-- Equation(s):
-- \codeout[0]~5_combout\ = (\key_C[2]~reg0_q\ & (\key_C[1]~reg0_q\ & \key_C[3]~reg0_q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \key_C[2]~reg0_q\,
	datac => \key_C[1]~reg0_q\,
	datad => \key_C[3]~reg0_q\,
	combout => \codeout[0]~5_combout\);

-- Location: LCCOMB_X26_Y42_N28
\Selector5~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Selector5~0_combout\ = (\key_C[2]~reg0_q\ & ((\key_C[1]~reg0_q\ $ (!\key_R[1]~input_o\)) # (!\key_R[2]~input_o\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1001000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_C[1]~reg0_q\,
	datab => \key_R[1]~input_o\,
	datac => \key_C[2]~reg0_q\,
	datad => \key_R[2]~input_o\,
	combout => \Selector5~0_combout\);

-- Location: LCCOMB_X26_Y42_N0
\Selector5~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Selector5~1_combout\ = (\key_R[3]~input_o\ & (((\Selector5~0_combout\)) # (!\key_C[3]~reg0_q\))) # (!\key_R[3]~input_o\ & (((!\codeout[0]~5_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100111101000111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_C[3]~reg0_q\,
	datab => \key_R[3]~input_o\,
	datac => \codeout[0]~5_combout\,
	datad => \Selector5~0_combout\,
	combout => \Selector5~1_combout\);

-- Location: FF_X26_Y42_N1
\codeout[1]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Selector5~1_combout\,
	ena => \codeout[0]~4_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \codeout[1]~reg0_q\);

-- Location: LCCOMB_X26_Y42_N12
\Selector4~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Selector4~0_combout\ = ((\key_C[1]~reg0_q\ $ (!\key_R[1]~input_o\)) # (!\key_C[3]~reg0_q\)) # (!\key_C[2]~reg0_q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1001111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_C[1]~reg0_q\,
	datab => \key_R[1]~input_o\,
	datac => \key_C[2]~reg0_q\,
	datad => \key_C[3]~reg0_q\,
	combout => \Selector4~0_combout\);

-- Location: LCCOMB_X27_Y42_N20
\codeout[2]~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \codeout[2]~0_combout\ = (\key_R[2]~input_o\ & ((\Selector4~0_combout\))) # (!\key_R[2]~input_o\ & (\key_C[3]~reg0_q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110111001000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_R[2]~input_o\,
	datab => \key_C[3]~reg0_q\,
	datad => \Selector4~0_combout\,
	combout => \codeout[2]~0_combout\);

-- Location: LCCOMB_X27_Y42_N22
\codeout[0]~5_wirecell\ : cycloneiii_lcell_comb
-- Equation(s):
-- \codeout[0]~5_wirecell_combout\ = !\codeout[0]~5_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \codeout[0]~5_combout\,
	combout => \codeout[0]~5_wirecell_combout\);

-- Location: FF_X27_Y42_N21
\codeout[2]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \codeout[2]~0_combout\,
	asdata => \codeout[0]~5_wirecell_combout\,
	sload => \ALT_INV_key_R[3]~input_o\,
	ena => \codeout[0]~4_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \codeout[2]~reg0_q\);

-- Location: LCCOMB_X27_Y42_N18
\Selector3~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Selector3~0_combout\ = (\key_R[3]~input_o\ & ((\key_R[1]~input_o\ & (\key_C[3]~reg0_q\)) # (!\key_R[1]~input_o\ & ((!\codeout[0]~5_combout\))))) # (!\key_R[3]~input_o\ & (((\codeout[0]~5_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101010110100010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_R[3]~input_o\,
	datab => \key_R[1]~input_o\,
	datac => \key_C[3]~reg0_q\,
	datad => \codeout[0]~5_combout\,
	combout => \Selector3~0_combout\);

-- Location: LCCOMB_X27_Y42_N28
\Selector3~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Selector3~1_combout\ = (\Selector3~0_combout\) # ((!\key_R[2]~input_o\ & \key_R[3]~input_o\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111101010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_R[2]~input_o\,
	datac => \key_R[3]~input_o\,
	datad => \Selector3~0_combout\,
	combout => \Selector3~1_combout\);

-- Location: FF_X27_Y42_N29
\codeout[3]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Selector3~1_combout\,
	ena => \codeout[0]~4_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \codeout[3]~reg0_q\);

-- Location: LCCOMB_X27_Y42_N8
\Selector2~2\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Selector2~2_combout\ = (!\key_R[2]~input_o\ & (\key_R[3]~input_o\ & ((\key_C[2]~reg0_q\) # (!\key_C[3]~reg0_q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100010000000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_R[2]~input_o\,
	datab => \key_R[3]~input_o\,
	datac => \key_C[3]~reg0_q\,
	datad => \key_C[2]~reg0_q\,
	combout => \Selector2~2_combout\);

-- Location: LCCOMB_X27_Y42_N16
\Selector2~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Selector2~0_combout\ = (\key_C[3]~reg0_q\ & ((\key_C[1]~reg0_q\) # (!\key_C[2]~reg0_q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000100010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_C[3]~reg0_q\,
	datab => \key_C[1]~reg0_q\,
	datad => \key_C[2]~reg0_q\,
	combout => \Selector2~0_combout\);

-- Location: LCCOMB_X27_Y42_N10
\Selector2~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Selector2~1_combout\ = (\key_R[2]~input_o\ & (\key_R[3]~input_o\ & ((\key_R[1]~input_o\) # (\Selector2~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010000010000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_R[2]~input_o\,
	datab => \key_R[1]~input_o\,
	datac => \key_R[3]~input_o\,
	datad => \Selector2~0_combout\,
	combout => \Selector2~1_combout\);

-- Location: LCCOMB_X27_Y42_N26
\Selector2~3\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Selector2~3_combout\ = (\Selector2~2_combout\) # ((\Selector2~1_combout\) # ((\codeout[0]~5_combout\ & !\key_R[3]~input_o\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111110010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \codeout[0]~5_combout\,
	datab => \key_R[3]~input_o\,
	datac => \Selector2~2_combout\,
	datad => \Selector2~1_combout\,
	combout => \Selector2~3_combout\);

-- Location: FF_X27_Y42_N27
\codeout[4]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Selector2~3_combout\,
	ena => \codeout[0]~4_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \codeout[4]~reg0_q\);

-- Location: LCCOMB_X27_Y42_N6
\codeout[5]~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \codeout[5]~1_combout\ = (\Equal0~1_combout\ & ((!\codeout[0]~5_combout\))) # (!\Equal0~1_combout\ & (\key_C[3]~reg0_q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010001011101110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_C[3]~reg0_q\,
	datab => \Equal0~1_combout\,
	datad => \codeout[0]~5_combout\,
	combout => \codeout[5]~1_combout\);

-- Location: FF_X27_Y42_N7
\codeout[5]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \codeout[5]~1_combout\,
	asdata => \Selector2~0_combout\,
	sload => \ALT_INV_key_R[3]~input_o\,
	ena => \codeout[0]~4_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \codeout[5]~reg0_q\);

-- Location: LCCOMB_X26_Y42_N22
\Selector0~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Selector0~0_combout\ = (\key_R[3]~input_o\ & ((\key_C[1]~reg0_q\ & ((\key_R[2]~input_o\))) # (!\key_C[1]~reg0_q\ & ((!\key_R[2]~input_o\) # (!\key_R[1]~input_o\))))) # (!\key_R[3]~input_o\ & (((\key_C[1]~reg0_q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111001001011010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_R[3]~input_o\,
	datab => \key_R[1]~input_o\,
	datac => \key_C[1]~reg0_q\,
	datad => \key_R[2]~input_o\,
	combout => \Selector0~0_combout\);

-- Location: LCCOMB_X26_Y42_N24
\Selector0~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Selector0~1_combout\ = (\Selector0~0_combout\) # (!\key_C[2]~reg0_q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111101010101",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_C[2]~reg0_q\,
	datad => \Selector0~0_combout\,
	combout => \Selector0~1_combout\);

-- Location: FF_X26_Y42_N25
\codeout[6]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Selector0~1_combout\,
	asdata => \key_R[3]~input_o\,
	sload => \ALT_INV_key_C[3]~reg0_q\,
	ena => \codeout[0]~4_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \codeout[6]~reg0_q\);

ww_key_C(0) <= \key_C[0]~output_o\;

ww_key_C(1) <= \key_C[1]~output_o\;

ww_key_C(2) <= \key_C[2]~output_o\;

ww_key_C(3) <= \key_C[3]~output_o\;

ww_codeout(0) <= \codeout[0]~output_o\;

ww_codeout(1) <= \codeout[1]~output_o\;

ww_codeout(2) <= \codeout[2]~output_o\;

ww_codeout(3) <= \codeout[3]~output_o\;

ww_codeout(4) <= \codeout[4]~output_o\;

ww_codeout(5) <= \codeout[5]~output_o\;

ww_codeout(6) <= \codeout[6]~output_o\;

ww_codeout(7) <= \codeout[7]~output_o\;
END structure;


